The present invention relates generally to the field of electronic test systems. More specifically, the invention provides an improved method and apparatus for performing probe tests on semiconductor wafers.
Various types of wafer test and probe equipment are well known to those of skill in the art, and are widely used in semiconductor manufacturing operations. Such equipment is used to provide electrical signals to a plurality of dies, generally formed on a semiconductor wafer, and to monitor the response of the dies to the electrical signals. Wafer test and probe equipment is made by a variety of manufacturers including, for example, Electroglas, Inc., KLA Instruments, Teradyne, Inc., Schlumberger Technologies, and LTX-Trillium.
Semiconductor wafer testing is normally conducted prior to wafer dicing and chip packaging. The wafer is placed on a prober chuck, indexed, and each die is tested. The testing operation normally involves placing a probe card with a number of probe tips in contact with a particular die at selected locations, such as, for example, the bond pads. Predetermined voltage patterns are then applied to the die, and the response of the die to the signals is monitored. If the die exhibits an appropriate response, the die is presumed to be "good." If the monitored response falls outside performance parameters, the die is either rejected, or appropriate remedial action is taken. Such wafer tests are performed on a wide variety of semiconductor products ranging from DRAMs and SRAMs to microprocessors.
Because modem semiconductor devices are being developed to operate at higher and higher speeds, "overhead" test techniques have been developed to keep signal transmission lines as short as possible. Short transmission lines reduce cross-talk between adjacent lines and eliminate other undesirable high frequency effects. In overhead testing techniques, a section of the tester referred to as the test head is positioned over the wafer under test and then docked to the prober. The interface between the test head and the wafer comprises a printed circuit board (Performance Interface Board or PIB), a plurality of downwardly extending spring loaded pins (Pogo.RTM. pins) and a probe card. The PIB and the Pogo pins are coupled to the test head which, when docked, causes the pins to come into contact with the probe card. The probe card is a custom printed circuit board which fores the connection between the Pogo pins and the probes (pins) which actually contact the wafer. Some systems use the weight of the test head to compress the Pogo pins against the probe card. Others employ a vacuum which forms a seal on the probe card to supply the necessary force. Still other systems have combined the PIB with the probe card to further reduce the signal transmission distances from the test head to the wafer. This has resulted in an increase in the size of stiffener/probe card assemblies.
While enjoying some measure of success, such prior systems have also encountered certain difficulties. One such difficulty is related to the fact that the arrangement of the bonding pad (used for testing) locations for various devices belonging to a family of products will differ from device type to device type, thus requiring different probe cards for testing each device type. For example, the arrangement of probes on a probe card for testing 1M DRAMs is radically different from the arrangement of probes on a probe card intended for testing of 4M DRAMs. Therefore, when the user of a prior system desires to switch the wafer product being tested, or if probe card gets damaged or dirty during testing, it becomes necessary to remove and replace the currently installed probe card. This is a time consuming and difficult task for a number of reasons. First, in many systems the probe card is mounted under the test head, which must be undocked before the probe card may be removed. This proves difficult because most test heads weigh between 250 and 750 pounds. Additionally, in most systems, the interface between the test head and the probe card must be disassembled and then reassembled. Finally, recalibration of probe card and test head positioning is required after replacement of a probe card.
As device density increases due to advances in semiconductor fabrication, probe card probes density also increases. Thus, the performance of the probe card interface system has become increasingly critical to successful device testing. In order to ensure proper contact between probe card probe tips and the device under test, significantly tight alignment must be maintained among the probes. In addition, at high densities, the probe card is commonly subjected to significant force while probes are in contact for testing. Because of the often delicate nature of probe card pins, such pressure frequently causes pin damage and/or misalignment. Thus, probe cards often require maintenance after repeated contacts with semiconductor wafers.
Conventionally, those of skill in the an have had no effective way of recording the operating history of a probe card. Therefore, contact failures only have been detected after the fact using, for example, a method such as the one disclosed by U.S. Pat. No. 5,019,771, the entire specification and drawings of which are herein incorporated by reference. Using such reactive methods, however, a probe card is replaced and/or repaired only after a failure has occurred. This results in undesirable system down time.
The problem of maintaining records on individual probe cards is made difficult by the fact that probe cards are frequently moved in and out of a testing system as described above. One solution involves manually labelling the various probe cards, and manually entering information regarding probe card usage on data sheets or into a computer. Unfortunately, this becomes difficult or impractical when large numbers of probe cards are in use. Additionally, the procedure is highly susceptible to human error.
Systems which present specific solutions to the above-described problems are disclosed in commonly assigned U.S. Pat. No. 5,254,939 for PROBE CARD SYSTEM AND METHOD, commonly assigned, copending U.S. patent application Ser. No. 08/089,874, filed on Jul. 9, 1993, as a continuation of the '939 patent, and commonly assigned, copending U.S. patent application Ser. No. 08/183,596, filed on Jan. 19, 1994, the entire specifications and drawings of which are herein incorporated by reference. The systems described in these documents provide excellent solutions to the above-described problems. However, because of specific industry needs, other solutions are needed.
In view of the foregoing, an improved system and method for conducting wafer probe tests is needed which provides a sturdy, simple, quick and reliable interface to load probe cards under a test head. An improved system and method for tracking individual probe card usage and performance as well as its alignment position under the test head is also desirable.